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(R)
M34S32
PRELIMINARY DATA
32K Serial I2C Bus EEPROM With User-Defined Read-Only Block and 32-Byte OTP Page
s
TWO WIRE I2C SERIAL INTERFACE, SUPPORTS 400kHz PROTOCOL COMPATIBLE WITH I2C EXTENDED ADDRESSING 1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE HARDWARE WRITE CONTROL USER-DEFINED READ-ONLY BLOCK 32 BYTES OTP PAGE BYTE and PAGE WRITE (up to 32 BYTES) BYTE, RANDOM and SEQUENTIAL READ MODES SELF TIMED PROGRAMING CYCLE AUTOMATIC ADDRESS INCREMENTING ENHANCED ESD and LATCH-UP PERFORMANCES
Figure 1. Delivery Forms
s
s s s s s s s s
8
8
1
1
PSDIP8 (BN) 0.25 mm Frame S08 (MN) 150 mil Width
s s s
Figure 2. Logic Diagram
DESCRIPTION The M34S32 is a 32K bit electrically erasable programmable memory (EEPROM), organized as 4096 x 8 bits. Table 1. Signal Names
SDA SCL WC WCR VCC VSS Serial Data Address Input/Output Serial Clock Write Control Write Control of Control Register Supply Voltage Ground
VCC
SCL WC WCR M34S32
SDA
VSS
AI02468
June 1998
This is a Preliminary Data. Details are subject to change without notice.
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M34S32
Figure 3. DIP Pin Connections Figure 4. SO Pin Connections
M34S32 NC NC WCR VSS 1 2 3 4 8 7 6 5
AI02448
M34S32 VCC WC SCL SDA NC NC WCR VSS 1 2 3 4 8 7 6 5
AI02449
VCC WC SCL SDA
Table 2. Absolute Maximum Ratings(1)
Symbol TA TSTG Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering TLEAD (SO8 package) (PSDIP8 package) Input or Output Voltages Supply Voltage (Human Body model) Electrostatic Discharge Voltage VESD Electrostatic Discharge Voltage
1. MIL-STD-883C, 3015.7 (100 pF, 1500 )
Parameter
Value -40 to 125 -65 to 150 40 sec 10 sec 215 260 -0.6 to 6.5 -0.3 to 6.5 4000
Unit C C C C V V V
VIO VCC
(Machine model)
2. EIAJ IC-121 (200 pF, 0 ) (Condition C)
500
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
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M34S32
DESCRIPTION (cont'd) The memory is compatible with the I2C extended addressing standard, two wire serial interface which uses a bi-directional data bus and serial clock. The memory carries a built-in 4 bit, unique device identification code (1010) corresponding to the I2C bus definition. The memory behaves as slave devices in the I2C protocol with all memory operations synchronized by the serial clock. Read and write operations are initiated by a START condition generated by the bus master. The START condition is followed by the Device Select Byte. This is a stream of 4 bits (the identification code 1010), then 3 bits of memory block access input, plus one read/write bit. The byte is finally terminated by an acknowledge bit. The M34S32 contains three memory blocks: the OTP page, the EEPROM block and the ROM block. The OTP (One Time Programmable) page is a page of 32 bytes, written once by the user. The OTP page is not located within the 32 Kbits EEPROM area. Once written, the OTP page cannot be modified by further write instructions. The ROM block resides inside the 32 Kbit EEPROM area. The size of the ROM block is defined (by the user) with the help of the Control Register. The OTP page is accessed with the Device Select Byte 1010001x, the EEPROM and ROM blocks are accessed with the Device Select Byte 1010000x. The control register is accessed with the Device Select Byte 1010100x (see Table 3). Table 3. Device Select Byte
Device Code Device Select Bit EEPROM and ROM access OTP Page access Control Register access b7 1 1 1 b6 0 0 0 b5 1 1 1 b4 0 0 0 Memory Block Access b3 0 0 1 b2 0 0 0 b1 0 1 0 RW b0 RW RW RW
When writing data to the memory it responds to the 8 bits received by asserting an acknowledge bit during the 9th bit time. When data is read by the bus master, it acknowledges the receipt of the data bytes in the same way. Data transfers are terminated with a STOP condition. Power On Reset: VCC lock out write protect. In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is implemented. Until the VCC voltage has reached the POR threshold value, the internal reset is active: all operations are disabled and the device will not respond to any command. In the same way, when VCC drops down from the operating voltage to below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL). The SCL input pin is used to synchronize all data in and out of the memory. A resistor can be connected from the SCL line to VCC to act as a pull up (see Figure 3) Serial Data (SDA). The SDA pin is bi-directional and is used to transfer data in or out of the memory. It is an open drain output that may be wireOR'ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from the SDA bus line to VCC (see Figure 3).
Table 4. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write 1 0 0 1 1 32 RW bit 1 0 1 reSTART, Device Select, RW = 1 As CURRENT or RANDOM Mode START, Device Select, RW = 0 START, Device Select, RW = 0 Data Bytes 1 Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address
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M34S32
Write Control (WC). The Write Control feature WC is useful to protect the contents of the whole EEPROM area from any erroneous erase/write cycle. It also protects the OTP page against the first write attempt. The Write Control signal polarity can be selected with the WCpol bit of the Control Register (see Table 13). When pin WC is unconnected, the WC input is internally read as VIL (see Table 5). When WC and WCpol are activating the Write Protection, Device Select and Address bytes are acknowledged; Data bytes are not acknowledged (see Figure 11). Write Control (WCR). In order to prevent spurious writes to the Control Register, the user can also make the Control Register Read Only (Write is inhibited). This is achieved by use of the WCR pin and the CRWD bit (see Table 14) : - - if CRWD bit = 0, the Control register can be modified regardless of the state of the WCR pin. - - if CRWD bit = 1, the Control register can be modified if the WCR pin is high. - - if CRWD bit = 1 and the WCR pin is low, the Control Register is Write Protected. DEVICE OPERATION I2C Bus Background The memory supports the extended addressing I2C protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master will always initiate a data transfer and will provide the serial clock for synchronisation. The memory is always a slave device in all communications. Start Condition. START is identified by a high to low transition of the SDA line while the clock SCL is stable in the high state. A START condition must precede any command for data transfer. Except during a programming cycle, the memory continuously monitors the SDA and SCL signals for a START condition and will not respond unless one is given. Stop Condition. STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory and the bus master. A STOP condition at the end of a Read command forces the stand-by state. A STOP condition at the end of a Write command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK). An acknowledge signal is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of the 8 bits of data. Data Input. During data input the memory samples the SDA bus signal on the rising edge of the clock SCL. For correct device operation the SDA signal must be stable during the clock low to high transition and the data must change ONLY when the SCL line is low. Device Selection. To start communication between the bus master and the slave memory, the master must initiate a START condition. The 8 bits sent after a START condition are made up of a Device Select Byte of 4 bits that identifies the device type, 3 memory block access bits and one bit for a READ (RW = 1) or WRITE (RW = 0) operation. There are two modes both for read and write. These are summarised in Table 4 and described hereafter. Communication between the master and the slave is ended with a STOP condition.
Table 5. Input Parameters (1) (TA = 25C, f = 400 kHz)
Symbol CIN CIN ZL ZH tLP Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC, WCR Input Impedance WC, WCR Input Impedance Low-pass filter input time constant (SDA and SCL) VIN 0.3 VCC VIN 0.7 VCC 5 500 100 Test Condition Min. Max. 8 6 20 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested in production.
4/18
M34S32 Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20
Maximum RP value (k)
16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
Table 6. DC Characteristics (TA = 0 to 70C, -40 to 85C; VCC = 4.5V to 5.5V, 2.5V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current ICC Supply Current (W series) ICC1 ICC2 VIL VIH VIL VIH VOL Output Low Voltage (W series) Stand-by Current Stand-by Current (W series) Input Low Voltage (WC, WCR) Input High Voltage (WC, WCR) Input Low Voltage (other pins) Input High Voltage (other pins) Output Low Voltage IOL = 3 mA, VCC = 5 V IOL = 2.1 mA, VCC = 2.5 V Test Condition 0 VIN VCC 0 VOUT VCC; SDA in Hi-Z VCC = 5 V; fC = 400 kHz (rise/fall time < 30 ns) VCC = 2.5 V; fC = 400 kHz (rise/fall time < 30 ns) VIN = VSS or VCC ; VCC = 5 V VIN = VSS or VCC ; VCC = 2.5 V - 0.3 VCC - 0.5 - 0.3 0.7 VCC Min. Max. 2 2 2 1 10 2 0.5 VCC + 1 0.3 VCC VCC + 1 0.4 0.4 Unit A A mA mA A A V V V V V V
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M34S32
Table 7. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50ns 0.2 VCC to 0.8 VCC
Figure 6. AC Testing Input/Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
0.3 VCC to 0.7 VCC
Table 8. AC Characteristics (TA = 0 to 70C, -40 to 85C; VCC = 4.5V to 5.5V, 2.5V to 5.5V)
M34S32 Symbol Alt. Parameter VCC = 4.5V to 5.5V Min. tCH1CH2 tCL1CL2 tDH1DH2 (1) tDL1DL2 (1) tCHDX (2) tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV (3) tQLQx fC tW tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Next Data Out Valid Data Out Hold Time Clock Frequency Write Time 20 20 600 600 600 0 1300 100 600 1300 200 200 400 10 900 Max. 300 300 300 300 20 20 600 600 600 0 1300 100 600 1300 200 200 400 10 900 VCC = 2.5V to 5.5V Min. Max. 300 300 300 300 ns ns ns ns ns ns ns s ns ns ns ns ns ns kHz ms Unit
Note: 1. Sampled only, not 100% tested in production. 2. For a reSTART condition, or following a write cycle. 3. The minimum value delays the falling/rising edge of SDA away from SCL=1 in order to avoid unwanted START and/or STOP conditions.
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M34S32
EEPROM Addressing. A data byte in the memory is addressed through 2 bytes of address information. The Most Significant Byte is sent first and the Least significant Byte is sent after. Bits b15 to b0 form the address of any byte of the memory. Bits b15 to b12 are don't care on the M34S32 series. Table 9. Most Significant Byte
b15 X b14 X b13 X b12 X b11 b10 b9 b8
Write Operations Following a START condition the master sends a Device Select Byte with the RW bit reset to 0. The memory acknowledges this and waits for 2 bytes of address. These 2 address bytes (8 bits each) provide access to any of the memory location. Writing in the memory may be inhibited with WC pin and WCpol bit (see Table 13 and Figure 11).
4. b15 to b12 are Don't Care.
Table 10. Least Significant Byte
b7 b6 b5 b4 b3 b2 b1 b0
Figure 7. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH tCLCH
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
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M34S32
Byte Write. In the Byte Write mode the master sends one data byte, which is acknowledged by the memory. The master then terminates the transfer by generating a STOP condition. Page Write. The Page Write mode allows up to 32 bytes to be written in a single write cycle, provided that they are all located in the same row of 32 bytes in the memory, that is the same Address bits (b12 to b5). The master sends one up to 32 bytes of data, which are each acknowledged by the memory. After each byte is transferred, the internal byte address counter (5 Least Significant Bits only) is incremented. The transfer is terminated by the master generating a STOP condition. Care must be taken to avoid address counter "roll-over" which could result in data being overwritten. Note that for any write mode, the generation by the master of the STOP condition starts the internal memory program cycle. This STOP condition will trigger an internal memory program cycle only if the STOP condition is internally decoded right after the ACK bit; any STOP condition decoded out of this "10th bit" time slot will not trigger the internal programming cycle. All inputs are disabled until the completion of this cycle and the Memory will not respond to any request.
Figure 8. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
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M34S32
Write to the Control Register The control register is accessed using a specific Device Select Byte (as described in Table 3, and as shown in Table 11 and Table 12). Table 11. Content of the Control Register
b7 b6 b5 X b4 B2 b3 B1 b2 B0 b1 X b0 X CRWD WCpol
B2,B1,B0. These bits control the size of the ROM block. Their initial, default state is 0, 0, 0. Table 15. Operation of the B2, B1 and B0 Bits
B2,B1,B0 0,0,0 0,0,1 0,1,0 0 1/64 1/32 1/16 1/8 1/4 1/2 1 ROM block size and location All bits are EEPROM ROM block=00h to 01FFh (512) ROM block=00h to 03FFh (1K) ROM block=00h to 07FFh (2K) ROM block=00h to 0FFFh (4K) ROM block=00h to 1FFFh (8K) ROM block=00h to 3FFFh (16K) All bits are ROM
Table 12. Default values
b7 0 b6 0 b5 X b4 0 b3 0 b2 0 b1 X b0 X
0,1,1 1,0,0 1,0,1 1,1,0 1,1,1
The meanings of the bits in Table 11 can be summarised as follows: WCpol. This bit controls the polarity of the WC input (to switch pin 7 between being a WC or WC input). The default (initial) state of this bit is 0. Table 13. Operation of the WCpol Bit
pin 7 = high pin 7 = low Write instructions are allowed in the EEPROM area, and the OTP page can be written once
In all cases, except when (B2,B1,B0)=(0,0,0), the selected area of EEPROM becomes read only (Write Protected) regardless of the status of the other bits and pins. However, the Control Register itself remains alterable in accordance with the status of WC, WCpol, WCR and CRWD. Write to the OTP Page The OTP page is accessed by addressing the device using the specific, Device Select Byte (as described in Table 3). The correct sequence for this instruction can be sketched out as follows: Start OTP Page Select(= 1010 0010) Ack Address (MSB) (= xxxx 0000) Ack Address (LSB) (= 0000 0000) Ack Data (= byte to be written) Ack ........ Data (= byte to be written) Ack Stop If one bit of the OTP Page Select differs from the above values, the OTP Page Select will NOT be acknowledged and the WRITE instruction will be ignored.
WCpol = 0
Whole EEPROM and OTP page are write protected
WCpol = 1
Write instructions are allowed in the EEPROM area, and the OTP page can be written once
Whole EEPROM and OTP page are write protected
CRWD. This is the Control Register Write Disable bit. When it is 0, pin 3 is a Don't Care input, and the control register is always writable. This is the default (initial) condition of this bit. Table 14. Operation of the CRWD Bit
pin 3 = high CRWD = 0 CRWD = 1 pin 3 = low
Control register is writable Control register is writable Control register is write protected (read only)
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M34S32
If one bit of the Address bytes (excluding the three most significant bits which are Don't Care) differs from the above values, the Address will be acknowledged, data will not be acknowledged and the WRITE instruction will be ignored. The Page Write instruction must start with the first byte that is located in the OTP page (address 0h), otherwise the instruction will be ignored. The first Write to the OTP page (whether it be a 1byte write, a 32-byte page write, or some size in between) will disable any further write in the OTP page. Let us suppose that byte N of the OTP page has just been addressed (for example because of a Write in the OTP page or a Random read in the OTP page). If the next instruction uses the Current Read Mode of the device, the first byte read in EEPROM will be in page 0, at address N+1 (or page 1, byte 0 if the last OTP byte addressed was at location 31). Figure 9. Write Cycle Polling using ACK
WRITE Cycle in Progress
Example of a correct sequence, leading to a 3byte write in the OTP page: Start 1010 0010 (OTP page select code) Ack 1111 0000 (upper address, MSB) Ack 0000 0000 (lower address, LSB) Ack 0100 1101 (write 3 bytes of data) Ack (in the OTP page) 1100 1010 Ack 0101 0011 Ack Stop
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M34Sxx
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI02418
10/18
M34S32
Example of an incorrect sequence, disabling the Write in the OTP page: Start 1010 0010 (OTP page select code) Ack xxxx 0000 (MSB address) Ack 0000 0100 (incorrect LSB address) Ack (acknowledged, but...) 0100 1101 (the attempts at) (no ack) (writing data to the) 1100 1010 (OTP page are) (no ack) (not acknowledged) 0101 0011 (no ack) Stop Figure 10. Write Modes Sequence with WC = 0 and WCpol = 0
WC ACK BYTE WRITE
START
Minimizing System Delay by Polling On ACK. During the internal Write cycle, the memory disables itself from the bus in order to copy the data from the internal latches to the memory cells. The maximum value of the Write time (tW) is given in the AC Characteristics table, this timing value may be reduced by an ACK polling sequence issued by the master. The sequence is: - Initial condition: a Write is in progress (see Figure 7). - Step 1: the Master issues a START condition followed by a Device Select Byte. (1st byte of the new instruction) - Step 2: if the memory is internally writing, no ACK will be returned. The Master goes back to Step1. If the memory has terminated the internal writing, it will issue an ACK. The memory is ready to receive the second part of the instruction (the first byte of this instruction was already sent during Step1).
ACK
ACK DATA IN
ACK
DEV SEL R/W
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE
START
ACK
ACK DATA IN 1
ACK DATA IN 2
DEV SEL R/W
BYTE ADDR
BYTE ADDR
WC (cont'd)
ACK PAGE WRITE (cont'd) DATA IN N
ACK
STOP
STOP
AI01106B
Note: 1. The device has the same behavior when WC = 1 and WCpol = 1.
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M34S32
Figure 11. Write Modes Sequence with WC = 1 and WCpol = 0
WC ACK BYTE WRITE
START
ACK
ACK
NO ACK DATA IN
STOP
DEV SEL R/W
BYTE ADDR
BYTE ADDR
WC ACK PAGE WRITE
START
ACK
ACK
NO ACK DATA IN 1 DATA IN 2
DEV SEL R/W
BYTE ADDR
BYTE ADDR
WC (cont'd) NO ACK PAGE WRITE (cont'd) NO ACK
DATA IN N
STOP
AI01120B
Note: 1. The device has the same behavior when WC = 0 and WCpol = 1.
Read Operations On delivery, the memory content is set at all "1"s (or FFh). Current Address Read. The memory has an internal address counter. Each time a byte is read, this counter is incremented. For the Current Address Read mode, following a START condition, the master sends a Device Select Byte with the RW bit set to 1. The memory acknowledges this and outputs the byte addressed by the internal address counter. This counter is then incremented. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. A Current Address Read in the OTP page is performed by sending the appropriate Device Select Byte, as described in Table 3.
Let us suppose, again, that byte N of the OTP page has just been addressed (for example because of a Write in the OTP page or a Random read in the OTP page). If the next instruction uses the Current Address Read Mode of the device, the first byte read in EEPROM will be in page 0, at address N+1 (or page 1, byte 0 if the last OTP byte addressed was at location 31). Random Address Read. A dummy write is performed to load the address into the address counter, see Figure 10. This is followed by another START condition from the master and the byte address repeated with the RW bit set to 1. The memory acknowledges this and outputs the byte addressed. The master does NOT acknowledge the byte output, but terminates the transfer with a STOP condition. Specific features of the Random Address read in the OTP page. This instruction must consist of the two sequences shown on page 14 (Sequence A followed by Sequence B).
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M34S32
Figure 12. Read Mode Sequences
ACK CURRENT ADDRESS READ
START
NO ACK DATA OUT
DEV SEL R/W
ACK RANDOM ADDRESS READ
START
ACK
STOP
ACK DEV SEL *
START
ACK
NO ACK DATA OUT
STOP
DEV SEL * R/W
BYTE ADDR
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ
START
ACK
ACK
NO ACK
DEV SEL R/W
DATA OUT 1
DATA OUT N
STOP
ACK SEQUENTIAL RANDOM READ
START
ACK
ACK DEV SEL *
START
ACK
ACK
DEV SEL *
BYTE ADDR R/W
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N
STOP
AI01105C
Note: 1. The seven most significant bits of the DEV SEL code of a Random Read (1st byte and 4th byte) must be identical.
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M34S32
Sequence A: Start OTP Page Select(= 1010 0010) Ack Address MSB (= xxxx 0000) Ack Address LSB (= 000x xxxx) Ack Sequence B: Start OTP Page Select(= 1010 0011) Ack Data Ack ........ Data (no Ack) Stop If one, or more bits of the Sequence A differ from the above values, the bytes that follow it will be acknowledged (or not) according to the same rules as for the WRITE IN OTP, and the RANDOM ADDRESS READ IN OTP will be ignored. Sequential Read. This mode can be initiated with either a Current Address Read or a Random Address Read. However, in this case the master DOES acknowledge the data byte output and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must NOT acknowledge the last byte output, but MUST generate a STOP condition. The output data is from consecutive byte addresses, with the internal byte address counter automatically incremented after each byte output. After a count of the last memory address, the address counter will "roll-over" and the memory will continue to output data. A Sequential Read in the OTP page is performed by sending the appropriate Device Select Byte, as described in Table 3. If a sequential read reaches the last location in the OTP page (address 1Fh), subsequent Sequential Reads will wrap round to the start, to address 00h. Acknowledge in Read Mode. In all read modes the memory waits for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to a stand-by state. APPLICATION HINTS ON HOW TO USE THE CONTROL REGISTER TOGETHER WITH THE / WCR PIN The application board can be designed in such a way that WCR pin is connected to VSS (directly or through a pull-down resistor). It should be noted that the WCR pin features an internal pull-down resistor allowing this input to be left unconnected. With such a P.C.B. (Printed Circuit Board), the device can be initialised according to following set-up sequence : 1. Write the data that is to be Write protected: - Write data in the area starting from address 00h up to the desired address. 2. Write in the Control Register (single byte write using the following bits): - Set B2, B1 and B0 values according to the ROM block size (as defined in Table 15) - Set WCpol according to the application needs. - Set CRWD bit to 1 Once the CRWD bit is set to 1, the control register becomes Write Protected. The only way to write again to the Control Register is to set the WCR pin high. This is possible by applying VCC to WCR if it was previously floating or connected to VSS through an external pull-down resistor. If WCR is shorted to VSS, the device needs to be de-soldered from the PCB. OTHER NOTES The WCR pin has an internal pull-down resistor. Connecting this pin to GND does not affect the power consumption, thus giving the M34S32 its lowest power consumption when it is in Protected mode. The OTP page may be programmed before or after the hardware protected mode has been set (by setting the CRWD bit). This allows the application MCU to program the OTP page either on the assembly line or during the operating life of the application. The WC pin (but not the WCR pin) may be driven dynamically by the MCU to increase the immunity to data corruption of the unprotected EEPROM area. This pin may alternatively be pulled to VCC or GND (depending on which is appropriate, according to the setting of the WCpol bit).
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M34S32
ORDERING INFORMATION SCHEME Devices are shipped from the factory with the memory content set at all "1"s (FFh). For a list of available options, refer to the current Memory Shortform Catalogue. For further information on any aspect of this device, please contact the ST Sales Office nearest to you. In general, the fields of the product number are made up as follows:
Example:
M 34 S 32 - W MN 1 T
AI02469
Capacity 32: 32 Kb (4Kx8)
Supply Voltage blank: 4.5 to 5.5 V W: 2.5 to 5.5 V
Package BN: PSDIP8 0.25 mm frame MN: SO8 150 mil body width
Temp. Range 1: 0 to 70 oC 6: -40 to 85 oC 5: -20 to 85 oC (see note 1)
Option T: Tape & Reel Packing
Note: 1. Temperature range 1 is available on request only.
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M34S32
Table 16. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 13. PSDIP8
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Note: Drawing is not to scale.
16/18
M34S32
Table 17. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 14. SO8a
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Note: Drawing is not to scale.
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M34S32
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